140 lines
4.2 KiB
C++
140 lines
4.2 KiB
C++
// This file is part of the Luau programming language and is licensed under MIT License; see LICENSE.txt for details
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#pragma once
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#include "Luau/Common.h"
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#include <bitset>
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#include <utility>
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#include <vector>
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#include <stdint.h>
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namespace Luau
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{
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namespace CodeGen
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{
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struct IrBlock;
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struct IrFunction;
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void updateUseCounts(IrFunction& function);
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void updateLastUseLocations(IrFunction& function);
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uint32_t getNextInstUse(IrFunction& function, uint32_t targetInstIdx, uint32_t startInstIdx);
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// Returns how many values are coming into the block (live in) and how many are coming out of the block (live out)
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std::pair<uint32_t, uint32_t> getLiveInOutValueCount(IrFunction& function, IrBlock& block);
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uint32_t getLiveInValueCount(IrFunction& function, IrBlock& block);
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uint32_t getLiveOutValueCount(IrFunction& function, IrBlock& block);
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struct RegisterSet
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{
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std::bitset<256> regs;
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// If variadic sequence is active, we track register from which it starts
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bool varargSeq = false;
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uint8_t varargStart = 0;
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};
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void requireVariadicSequence(RegisterSet& sourceRs, const RegisterSet& defRs, uint8_t varargStart);
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struct BlockOrdering
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{
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uint32_t depth = 0;
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uint32_t preOrder = ~0u;
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uint32_t postOrder = ~0u;
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bool visited = false;
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};
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struct CfgInfo
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{
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std::vector<uint32_t> predecessors;
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std::vector<uint32_t> predecessorsOffsets;
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std::vector<uint32_t> successors;
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std::vector<uint32_t> successorsOffsets;
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// Immediate dominators (unique parent in the dominator tree)
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std::vector<uint32_t> idoms;
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// Children in the dominator tree
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std::vector<uint32_t> domChildren;
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std::vector<uint32_t> domChildrenOffsets;
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std::vector<BlockOrdering> domOrdering;
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// VM registers that are live when the block is entered
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// Additionally, an active variadic sequence can exist at the entry of the block
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std::vector<RegisterSet> in;
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// VM registers that are defined inside the block
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// It can also contain a variadic sequence definition if that hasn't been consumed inside the block
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// Note that this means that checking 'def' set might not be enough to say that register has not been written to
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std::vector<RegisterSet> def;
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// VM registers that are coming out from the block
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// These might be registers that are defined inside the block or have been defined at the entry of the block
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// Additionally, an active variadic sequence can exist at the exit of the block
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std::vector<RegisterSet> out;
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// VM registers captured by nested closures
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// This set can never have an active variadic sequence
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RegisterSet captured;
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};
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// A quick refresher on dominance and dominator trees:
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// * If A is a dominator of B (A dom B), you can never execute B without executing A first
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// * A is a strict dominator of B (A sdom B) is similar to previous one but A != B
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// * Immediate dominator node N (idom N) is a unique node T so that T sdom N,
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// but T does not strictly dominate any other node that dominates N.
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// * Dominance frontier is a set of nodes where dominance of a node X ends.
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// In practice this is where values established by node X might no longer hold because of join edges from other nodes coming in.
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// This is also where PHI instructions in SSA are placed.
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void computeCfgImmediateDominators(IrFunction& function);
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void computeCfgDominanceTreeChildren(IrFunction& function);
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// Function used to update all CFG data
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void computeCfgInfo(IrFunction& function);
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struct BlockIteratorWrapper
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{
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const uint32_t* itBegin = nullptr;
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const uint32_t* itEnd = nullptr;
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bool empty() const
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{
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return itBegin == itEnd;
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}
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size_t size() const
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{
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return size_t(itEnd - itBegin);
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}
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const uint32_t* begin() const
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{
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return itBegin;
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}
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const uint32_t* end() const
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{
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return itEnd;
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}
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uint32_t operator[](size_t pos) const
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{
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LUAU_ASSERT(pos < size_t(itEnd - itBegin));
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return itBegin[pos];
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}
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};
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BlockIteratorWrapper predecessors(const CfgInfo& cfg, uint32_t blockIdx);
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BlockIteratorWrapper successors(const CfgInfo& cfg, uint32_t blockIdx);
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BlockIteratorWrapper domChildren(const CfgInfo& cfg, uint32_t blockIdx);
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} // namespace CodeGen
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} // namespace Luau
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