692 lines
22 KiB
C++
692 lines
22 KiB
C++
// This file is part of the Luau programming language and is licensed under MIT License; see LICENSE.txt for details
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#include "Luau/IrAnalysis.h"
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#include "Luau/DenseHash.h"
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#include "Luau/IrData.h"
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#include "Luau/IrUtils.h"
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#include "lobject.h"
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#include <bitset>
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#include <stddef.h>
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namespace Luau
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{
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namespace CodeGen
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{
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void updateUseCounts(IrFunction& function)
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{
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std::vector<IrBlock>& blocks = function.blocks;
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std::vector<IrInst>& instructions = function.instructions;
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for (IrBlock& block : blocks)
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block.useCount = 0;
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for (IrInst& inst : instructions)
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inst.useCount = 0;
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auto checkOp = [&](IrOp op) {
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if (op.kind == IrOpKind::Inst)
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{
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IrInst& target = instructions[op.index];
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LUAU_ASSERT(target.useCount < 0xffff);
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target.useCount++;
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}
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else if (op.kind == IrOpKind::Block)
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{
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IrBlock& target = blocks[op.index];
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LUAU_ASSERT(target.useCount < 0xffff);
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target.useCount++;
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}
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};
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for (IrInst& inst : instructions)
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{
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checkOp(inst.a);
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checkOp(inst.b);
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checkOp(inst.c);
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checkOp(inst.d);
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checkOp(inst.e);
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checkOp(inst.f);
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}
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}
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void updateLastUseLocations(IrFunction& function)
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{
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std::vector<IrInst>& instructions = function.instructions;
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for (IrInst& inst : instructions)
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inst.lastUse = 0;
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for (size_t instIdx = 0; instIdx < instructions.size(); ++instIdx)
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{
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IrInst& inst = instructions[instIdx];
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auto checkOp = [&](IrOp op) {
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if (op.kind == IrOpKind::Inst)
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instructions[op.index].lastUse = uint32_t(instIdx);
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};
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if (isPseudo(inst.cmd))
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continue;
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checkOp(inst.a);
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checkOp(inst.b);
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checkOp(inst.c);
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checkOp(inst.d);
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checkOp(inst.e);
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checkOp(inst.f);
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}
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}
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uint32_t getNextInstUse(IrFunction& function, uint32_t targetInstIdx, uint32_t startInstIdx)
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{
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LUAU_ASSERT(startInstIdx < function.instructions.size());
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IrInst& targetInst = function.instructions[targetInstIdx];
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for (uint32_t i = startInstIdx; i <= targetInst.lastUse; i++)
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{
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IrInst& inst = function.instructions[i];
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if (isPseudo(inst.cmd))
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continue;
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if (inst.a.kind == IrOpKind::Inst && inst.a.index == targetInstIdx)
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return i;
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if (inst.b.kind == IrOpKind::Inst && inst.b.index == targetInstIdx)
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return i;
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if (inst.c.kind == IrOpKind::Inst && inst.c.index == targetInstIdx)
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return i;
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if (inst.d.kind == IrOpKind::Inst && inst.d.index == targetInstIdx)
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return i;
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if (inst.e.kind == IrOpKind::Inst && inst.e.index == targetInstIdx)
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return i;
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if (inst.f.kind == IrOpKind::Inst && inst.f.index == targetInstIdx)
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return i;
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}
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// There must be a next use since there is the last use location
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LUAU_ASSERT(!"Failed to find next use");
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return targetInst.lastUse;
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}
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std::pair<uint32_t, uint32_t> getLiveInOutValueCount(IrFunction& function, IrBlock& block)
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{
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uint32_t liveIns = 0;
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uint32_t liveOuts = 0;
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auto checkOp = [&](IrOp op) {
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if (op.kind == IrOpKind::Inst)
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{
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if (op.index >= block.start && op.index <= block.finish)
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liveOuts--;
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else
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liveIns++;
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}
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};
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for (uint32_t instIdx = block.start; instIdx <= block.finish; instIdx++)
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{
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IrInst& inst = function.instructions[instIdx];
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if (isPseudo(inst.cmd))
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continue;
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liveOuts += inst.useCount;
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checkOp(inst.a);
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checkOp(inst.b);
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checkOp(inst.c);
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checkOp(inst.d);
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checkOp(inst.e);
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checkOp(inst.f);
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}
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return std::make_pair(liveIns, liveOuts);
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}
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uint32_t getLiveInValueCount(IrFunction& function, IrBlock& block)
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{
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return getLiveInOutValueCount(function, block).first;
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}
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uint32_t getLiveOutValueCount(IrFunction& function, IrBlock& block)
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{
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return getLiveInOutValueCount(function, block).second;
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}
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void requireVariadicSequence(RegisterSet& sourceRs, const RegisterSet& defRs, uint8_t varargStart)
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{
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if (!defRs.varargSeq)
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{
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// Peel away registers from variadic sequence that we define
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while (defRs.regs.test(varargStart))
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varargStart++;
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LUAU_ASSERT(!sourceRs.varargSeq || sourceRs.varargStart == varargStart);
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sourceRs.varargSeq = true;
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sourceRs.varargStart = varargStart;
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}
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else
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{
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// Variadic use sequence might include registers before def sequence
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for (int i = varargStart; i < defRs.varargStart; i++)
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{
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if (!defRs.regs.test(i))
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sourceRs.regs.set(i);
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}
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}
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}
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static RegisterSet computeBlockLiveInRegSet(IrFunction& function, const IrBlock& block, RegisterSet& defRs, std::bitset<256>& capturedRegs)
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{
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RegisterSet inRs;
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auto def = [&](IrOp op, int offset = 0) {
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defRs.regs.set(vmRegOp(op) + offset, true);
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};
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auto use = [&](IrOp op, int offset = 0) {
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if (!defRs.regs.test(vmRegOp(op) + offset))
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inRs.regs.set(vmRegOp(op) + offset, true);
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};
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auto maybeDef = [&](IrOp op) {
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if (op.kind == IrOpKind::VmReg)
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defRs.regs.set(vmRegOp(op), true);
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};
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auto maybeUse = [&](IrOp op) {
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if (op.kind == IrOpKind::VmReg)
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{
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if (!defRs.regs.test(vmRegOp(op)))
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inRs.regs.set(vmRegOp(op), true);
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}
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};
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auto defVarargs = [&](uint8_t varargStart) {
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defRs.varargSeq = true;
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defRs.varargStart = varargStart;
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};
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auto useVarargs = [&](uint8_t varargStart) {
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requireVariadicSequence(inRs, defRs, varargStart);
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// Variadic sequence has been consumed
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defRs.varargSeq = false;
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defRs.varargStart = 0;
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};
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auto defRange = [&](int start, int count) {
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if (count == -1)
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{
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defVarargs(start);
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}
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else
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{
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for (int i = start; i < start + count; i++)
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defRs.regs.set(i, true);
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}
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};
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auto useRange = [&](int start, int count) {
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if (count == -1)
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{
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useVarargs(start);
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}
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else
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{
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for (int i = start; i < start + count; i++)
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{
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if (!defRs.regs.test(i))
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inRs.regs.set(i, true);
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}
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}
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};
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for (uint32_t instIdx = block.start; instIdx <= block.finish; instIdx++)
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{
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const IrInst& inst = function.instructions[instIdx];
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// For correct analysis, all instruction uses must be handled before handling the definitions
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switch (inst.cmd)
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{
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case IrCmd::LOAD_TAG:
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case IrCmd::LOAD_POINTER:
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case IrCmd::LOAD_DOUBLE:
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case IrCmd::LOAD_INT:
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case IrCmd::LOAD_TVALUE:
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maybeUse(inst.a); // Argument can also be a VmConst
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break;
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case IrCmd::STORE_TAG:
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case IrCmd::STORE_POINTER:
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case IrCmd::STORE_DOUBLE:
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case IrCmd::STORE_INT:
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case IrCmd::STORE_VECTOR:
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case IrCmd::STORE_TVALUE:
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maybeDef(inst.a); // Argument can also be a pointer value
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break;
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case IrCmd::JUMP_IF_TRUTHY:
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case IrCmd::JUMP_IF_FALSY:
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use(inst.a);
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break;
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case IrCmd::JUMP_CMP_ANY:
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use(inst.a);
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use(inst.b);
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break;
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// A <- B, C
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case IrCmd::DO_ARITH:
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case IrCmd::GET_TABLE:
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use(inst.b);
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maybeUse(inst.c); // Argument can also be a VmConst
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def(inst.a);
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break;
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case IrCmd::SET_TABLE:
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use(inst.a);
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use(inst.b);
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maybeUse(inst.c); // Argument can also be a VmConst
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break;
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// A <- B
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case IrCmd::DO_LEN:
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use(inst.b);
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def(inst.a);
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break;
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case IrCmd::GET_IMPORT:
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def(inst.a);
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break;
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case IrCmd::CONCAT:
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useRange(vmRegOp(inst.a), function.uintOp(inst.b));
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defRange(vmRegOp(inst.a), function.uintOp(inst.b));
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break;
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case IrCmd::GET_UPVALUE:
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def(inst.a);
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break;
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case IrCmd::SET_UPVALUE:
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use(inst.b);
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break;
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case IrCmd::PREPARE_FORN:
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use(inst.a);
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use(inst.b);
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use(inst.c);
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def(inst.a);
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def(inst.b);
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def(inst.c);
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break;
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case IrCmd::INTERRUPT:
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break;
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case IrCmd::BARRIER_OBJ:
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case IrCmd::BARRIER_TABLE_FORWARD:
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use(inst.b);
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break;
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case IrCmd::CLOSE_UPVALS:
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// Closing an upvalue should be counted as a register use (it copies the fresh register value)
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// But we lack the required information about the specific set of registers that are affected
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// Because we don't plan to optimize captured registers atm, we skip full dataflow analysis for them right now
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break;
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case IrCmd::CAPTURE:
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maybeUse(inst.a);
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if (function.uintOp(inst.b) == 1)
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capturedRegs.set(vmRegOp(inst.a), true);
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break;
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case IrCmd::SETLIST:
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use(inst.b);
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useRange(vmRegOp(inst.c), function.intOp(inst.d));
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break;
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case IrCmd::CALL:
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use(inst.a);
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useRange(vmRegOp(inst.a) + 1, function.intOp(inst.b));
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defRange(vmRegOp(inst.a), function.intOp(inst.c));
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break;
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case IrCmd::RETURN:
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useRange(vmRegOp(inst.a), function.intOp(inst.b));
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break;
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// TODO: FASTCALL is more restrictive than INVOKE_FASTCALL; we should either determine the exact semantics, or rework it
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case IrCmd::FASTCALL:
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case IrCmd::INVOKE_FASTCALL:
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if (int count = function.intOp(inst.e); count != -1)
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{
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if (count >= 3)
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{
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LUAU_ASSERT(inst.d.kind == IrOpKind::VmReg && vmRegOp(inst.d) == vmRegOp(inst.c) + 1);
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useRange(vmRegOp(inst.c), count);
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}
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else
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{
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if (count >= 1)
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use(inst.c);
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if (count >= 2)
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maybeUse(inst.d); // Argument can also be a VmConst
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}
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}
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else
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{
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useVarargs(vmRegOp(inst.c));
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}
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// Multiple return sequences (count == -1) are defined by ADJUST_STACK_TO_REG
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if (int count = function.intOp(inst.f); count != -1)
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defRange(vmRegOp(inst.b), count);
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break;
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case IrCmd::FORGLOOP:
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// First register is not used by instruction, we check that it's still 'nil' with CHECK_TAG
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use(inst.a, 1);
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use(inst.a, 2);
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def(inst.a, 2);
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defRange(vmRegOp(inst.a) + 3, function.intOp(inst.b));
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break;
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case IrCmd::FORGLOOP_FALLBACK:
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useRange(vmRegOp(inst.a), 3);
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def(inst.a, 2);
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defRange(vmRegOp(inst.a) + 3, uint8_t(function.intOp(inst.b))); // ignore most significant bit
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break;
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case IrCmd::FORGPREP_XNEXT_FALLBACK:
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use(inst.b);
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break;
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case IrCmd::FALLBACK_GETGLOBAL:
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def(inst.b);
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break;
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case IrCmd::FALLBACK_SETGLOBAL:
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use(inst.b);
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break;
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case IrCmd::FALLBACK_GETTABLEKS:
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use(inst.c);
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def(inst.b);
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break;
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case IrCmd::FALLBACK_SETTABLEKS:
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use(inst.b);
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use(inst.c);
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break;
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case IrCmd::FALLBACK_NAMECALL:
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use(inst.c);
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defRange(vmRegOp(inst.b), 2);
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break;
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case IrCmd::FALLBACK_PREPVARARGS:
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// No effect on explicitly referenced registers
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break;
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case IrCmd::FALLBACK_GETVARARGS:
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defRange(vmRegOp(inst.b), function.intOp(inst.c));
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break;
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case IrCmd::FALLBACK_NEWCLOSURE:
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def(inst.b);
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break;
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case IrCmd::FALLBACK_DUPCLOSURE:
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def(inst.b);
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break;
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case IrCmd::FALLBACK_FORGPREP:
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use(inst.b);
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defRange(vmRegOp(inst.b), 3);
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break;
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case IrCmd::ADJUST_STACK_TO_REG:
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defRange(vmRegOp(inst.a), -1);
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break;
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case IrCmd::ADJUST_STACK_TO_TOP:
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// While this can be considered to be a vararg consumer, it is already handled in fastcall instructions
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break;
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default:
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// All instructions which reference registers have to be handled explicitly
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LUAU_ASSERT(inst.a.kind != IrOpKind::VmReg);
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LUAU_ASSERT(inst.b.kind != IrOpKind::VmReg);
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LUAU_ASSERT(inst.c.kind != IrOpKind::VmReg);
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LUAU_ASSERT(inst.d.kind != IrOpKind::VmReg);
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LUAU_ASSERT(inst.e.kind != IrOpKind::VmReg);
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LUAU_ASSERT(inst.f.kind != IrOpKind::VmReg);
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break;
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}
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}
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return inRs;
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}
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// The algorithm used here is commonly known as backwards data-flow analysis.
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// For each block, we track 'upward-exposed' (live-in) uses of registers - a use of a register that hasn't been defined in the block yet.
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// We also track the set of registers that were defined in the block.
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// When initial live-in sets of registers are computed, propagation of those uses upwards through predecessors is performed.
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// If predecessor doesn't define the register, we have to add it to the live-in set.
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// Extending the set of live-in registers of a block requires re-checking of that block.
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// Propagation runs iteratively, using a worklist of blocks to visit until a fixed point is reached.
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// This algorithm can be easily extended to cover phi instructions, but we don't use those yet.
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static void computeCfgLiveInOutRegSets(IrFunction& function)
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{
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CfgInfo& info = function.cfg;
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// Clear existing data
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// 'in' and 'captured' data is not cleared because it will be overwritten below
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info.def.clear();
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info.out.clear();
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// Try to compute Luau VM register use-def info
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info.in.resize(function.blocks.size());
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info.def.resize(function.blocks.size());
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info.out.resize(function.blocks.size());
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// Captured registers are tracked for the whole function
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// It should be possible to have a more precise analysis for them in the future
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std::bitset<256> capturedRegs;
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// First we compute live-in set of each block
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for (size_t blockIdx = 0; blockIdx < function.blocks.size(); blockIdx++)
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{
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const IrBlock& block = function.blocks[blockIdx];
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if (block.kind == IrBlockKind::Dead)
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continue;
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info.in[blockIdx] = computeBlockLiveInRegSet(function, block, info.def[blockIdx], capturedRegs);
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}
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info.captured.regs = capturedRegs;
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// With live-in sets ready, we can arrive at a fixed point for both in/out registers by requesting required registers from predecessors
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std::vector<uint32_t> worklist;
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std::vector<uint8_t> inWorklist;
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inWorklist.resize(function.blocks.size(), false);
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// We will have to visit each block at least once, so we add all of them to the worklist immediately
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for (size_t blockIdx = 0; blockIdx < function.blocks.size(); blockIdx++)
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{
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const IrBlock& block = function.blocks[blockIdx];
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if (block.kind == IrBlockKind::Dead)
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continue;
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worklist.push_back(uint32_t(blockIdx));
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inWorklist[blockIdx] = true;
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}
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while (!worklist.empty())
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{
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uint32_t blockIdx = worklist.back();
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worklist.pop_back();
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inWorklist[blockIdx] = false;
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IrBlock& curr = function.blocks[blockIdx];
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RegisterSet& inRs = info.in[blockIdx];
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RegisterSet& defRs = info.def[blockIdx];
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RegisterSet& outRs = info.out[blockIdx];
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// Current block has to provide all registers in successor blocks
|
|
BlockIteratorWrapper successorsIt = successors(info, blockIdx);
|
|
for (uint32_t succIdx : successorsIt)
|
|
{
|
|
IrBlock& succ = function.blocks[succIdx];
|
|
|
|
// This is a step away from the usual definition of live range flow through CFG
|
|
// Exit from a regular block to a fallback block is not considered a block terminator
|
|
// This is because fallback blocks define an alternative implementation of the same operations
|
|
// This can cause the current block to define more registers that actually were available at fallback entry
|
|
if (curr.kind != IrBlockKind::Fallback && succ.kind == IrBlockKind::Fallback)
|
|
{
|
|
// If this is the only successor, this skip will not be valid
|
|
LUAU_ASSERT(successorsIt.size() != 1);
|
|
continue;
|
|
}
|
|
|
|
const RegisterSet& succRs = info.in[succIdx];
|
|
|
|
outRs.regs |= succRs.regs;
|
|
|
|
if (succRs.varargSeq)
|
|
{
|
|
LUAU_ASSERT(!outRs.varargSeq || outRs.varargStart == succRs.varargStart);
|
|
|
|
outRs.varargSeq = true;
|
|
outRs.varargStart = succRs.varargStart;
|
|
}
|
|
}
|
|
|
|
RegisterSet oldInRs = inRs;
|
|
|
|
// If current block didn't define a live-out, it has to be live-in
|
|
inRs.regs |= outRs.regs & ~defRs.regs;
|
|
|
|
if (outRs.varargSeq)
|
|
requireVariadicSequence(inRs, defRs, outRs.varargStart);
|
|
|
|
// If we have new live-ins, we have to notify all predecessors
|
|
// We don't allow changes to the start of the variadic sequence, so we skip checking that member
|
|
if (inRs.regs != oldInRs.regs || inRs.varargSeq != oldInRs.varargSeq)
|
|
{
|
|
for (uint32_t predIdx : predecessors(info, blockIdx))
|
|
{
|
|
if (!inWorklist[predIdx])
|
|
{
|
|
worklist.push_back(predIdx);
|
|
inWorklist[predIdx] = true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// If Proto data is available, validate that entry block arguments match required registers
|
|
if (function.proto)
|
|
{
|
|
RegisterSet& entryIn = info.in[0];
|
|
|
|
LUAU_ASSERT(!entryIn.varargSeq);
|
|
|
|
for (size_t i = 0; i < entryIn.regs.size(); i++)
|
|
LUAU_ASSERT(!entryIn.regs.test(i) || i < function.proto->numparams);
|
|
}
|
|
}
|
|
|
|
static void computeCfgBlockEdges(IrFunction& function)
|
|
{
|
|
CfgInfo& info = function.cfg;
|
|
|
|
// Clear existing data
|
|
info.predecessorsOffsets.clear();
|
|
info.successorsOffsets.clear();
|
|
|
|
// Compute predecessors block edges
|
|
info.predecessorsOffsets.reserve(function.blocks.size());
|
|
info.successorsOffsets.reserve(function.blocks.size());
|
|
|
|
int edgeCount = 0;
|
|
|
|
for (const IrBlock& block : function.blocks)
|
|
{
|
|
info.predecessorsOffsets.push_back(edgeCount);
|
|
edgeCount += block.useCount;
|
|
}
|
|
|
|
info.predecessors.resize(edgeCount);
|
|
info.successors.resize(edgeCount);
|
|
|
|
edgeCount = 0;
|
|
|
|
for (size_t blockIdx = 0; blockIdx < function.blocks.size(); blockIdx++)
|
|
{
|
|
const IrBlock& block = function.blocks[blockIdx];
|
|
|
|
info.successorsOffsets.push_back(edgeCount);
|
|
|
|
if (block.kind == IrBlockKind::Dead)
|
|
continue;
|
|
|
|
for (uint32_t instIdx = block.start; instIdx <= block.finish; instIdx++)
|
|
{
|
|
const IrInst& inst = function.instructions[instIdx];
|
|
|
|
auto checkOp = [&](IrOp op) {
|
|
if (op.kind == IrOpKind::Block)
|
|
{
|
|
// We use a trick here, where we use the starting offset of the predecessor list as the position where to write next predecessor
|
|
// The values will be adjusted back in a separate loop later
|
|
info.predecessors[info.predecessorsOffsets[op.index]++] = uint32_t(blockIdx);
|
|
|
|
info.successors[edgeCount++] = op.index;
|
|
}
|
|
};
|
|
|
|
checkOp(inst.a);
|
|
checkOp(inst.b);
|
|
checkOp(inst.c);
|
|
checkOp(inst.d);
|
|
checkOp(inst.e);
|
|
checkOp(inst.f);
|
|
}
|
|
}
|
|
|
|
// Offsets into the predecessor list were used as iterators in the previous loop
|
|
// To adjust them back, block use count is subtracted (predecessor count is equal to how many uses block has)
|
|
for (size_t blockIdx = 0; blockIdx < function.blocks.size(); blockIdx++)
|
|
{
|
|
const IrBlock& block = function.blocks[blockIdx];
|
|
|
|
info.predecessorsOffsets[blockIdx] -= block.useCount;
|
|
}
|
|
}
|
|
|
|
void computeCfgInfo(IrFunction& function)
|
|
{
|
|
computeCfgBlockEdges(function);
|
|
computeCfgLiveInOutRegSets(function);
|
|
}
|
|
|
|
BlockIteratorWrapper predecessors(const CfgInfo& cfg, uint32_t blockIdx)
|
|
{
|
|
LUAU_ASSERT(blockIdx < cfg.predecessorsOffsets.size());
|
|
|
|
uint32_t start = cfg.predecessorsOffsets[blockIdx];
|
|
uint32_t end = blockIdx + 1 < cfg.predecessorsOffsets.size() ? cfg.predecessorsOffsets[blockIdx + 1] : uint32_t(cfg.predecessors.size());
|
|
|
|
return BlockIteratorWrapper{cfg.predecessors.data() + start, cfg.predecessors.data() + end};
|
|
}
|
|
|
|
BlockIteratorWrapper successors(const CfgInfo& cfg, uint32_t blockIdx)
|
|
{
|
|
LUAU_ASSERT(blockIdx < cfg.successorsOffsets.size());
|
|
|
|
uint32_t start = cfg.successorsOffsets[blockIdx];
|
|
uint32_t end = blockIdx + 1 < cfg.successorsOffsets.size() ? cfg.successorsOffsets[blockIdx + 1] : uint32_t(cfg.successors.size());
|
|
|
|
return BlockIteratorWrapper{cfg.successors.data() + start, cfg.successors.data() + end};
|
|
}
|
|
|
|
} // namespace CodeGen
|
|
} // namespace Luau
|